M.Tech Digital VLSI Design Projects

M.Tech ECE VLSI Projects List 2021

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S.No. List of the Project Base. Paper Abstract
1. Design of Area-Efficient and Highly Reliable RHBD I0T Memory Cell for Aerospace Applications Download Download
2. Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits Download Download
3. Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion Download Download
4. A Low-Power High-Speed Comparator for Precise Applications Download Download
5. A High-Performance Gated Voltage Level Translator with Integrated Multiplexer Download Download
6. High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop Download Download
7. Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis Download Download
8. High-Performance Ternary Adder using CNTFET Download Download
9. Probability-Driven Multibit Flip-Flop Integration with Clock Gating Download Download
10. High-performance engineered gate transistor-based compact digital circuits Download Download
11. Design and Low Power Magnitude Comparator Download Download
12. A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications Download Download
13. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs Download Download
14. Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers  Download Download
15. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders  Download Download
16. Delay Analysis for Current Mode Threshold Logic Gate Designs Download Download
17. 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage Download Download
18. A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell  Download Download
19. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Download Download
20. Design for Testability of Sleep Convention Logic  Download Download
21. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Download Download
22. Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Download Download
23. Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology Download Download
24. Low-power And Fast Full Adder By Exploring New XOR And XNOR Gates Download Download
25. A Low Power And High Speed Voltage Level Shifter Based On A Regulated Cross Coupled Pull Up Network Download Download
26. Hybrid Logical Effort For Hybrid Logic Style Full Adders In Multistage Structures Download Download
27. Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique For On-chip Digital Filter Applications Download Download
28. Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors Download Download
29. Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM Download Download
30. Design And Characterization Of SEU Hardened Circuits For SRAM-based FPGA Download Download
31. Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops Download Download
32. Low Leakage Clock Tree With Dual-threshold- Voltage Split Input–output Repeaters Download Download
33. Hybrid Logical Effort For Hybrid Logic Style Full Adders In Multistage Structures Download Download
34. Radiation-hardened 14t SRAM Bitcell With Speed And Power Optimized For Space Application Download Download
35. A 7t Security Oriented SRAM Bitcell Download Download
36. Column-selection-enabled 10t SRAM Utilizing Shared Diff-vdd Write And Dropped-vdd Read For Power Reduction Download Download
37. Three-dimensional Monolithic FinFET-based 8T SRAM Cell Design For Enhanced Read Time And Low Leakage Download Download
38. Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits Download Download
39. Energy Efficient Single-ended 6T SRAM For Multimedia Applications Download Download
40. Design Of Area-efficient And Highly Reliable Rhbd 10t Memory Cell For Aerospace Applications Download Download
41. Power Efficient And Reliable Nonvolatile TCAM With Hi-PFO And Semi-complementary Driver Download Download
42. Optimized Memristor-Based Multipliers Download Download
43. The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel IndexSelection Download Download
44. Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design Download Download
45. A Very Compact CMOS Analog Multiplier For Application In CNN Synapses Download Download
46. Register -Less NULL Conventional Logic Download Download
47. A Fast-Locking, Low-Jitter Pulsewidth Control Loop for High-Speed ADC Download Download
48. Sense Amplifier Half-Buffer(SAHB):A Low-Power High-Performance Asynchronous Logic QDI Cell Template Download Download
49. A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme Download Download
50. Design And Characterization Of SEU Hardened Circuits For SRAM-based FPGA Download Download
51. A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS Download Download
52. A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC  Download Download
53. A 16-bit 2.0-psResolution Two-Step TDC in0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage WitBuilIn Coarse Gain Calibration Download Download
54. A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs Download Download
55. A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130 nm CMOS Download Download
56. Analysis,Comparison and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate Download Download
57. Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction Download Download
58. Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors Download Download
59. Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation Download Download
60. Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs Download Download
61. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS Download Download
62. Many-ObjectiveSizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-NoiseCellular Applications Download Download
63. Multiloop Control for Fast Transient DC–DC Converter Download Download
64. Probability-Driven Multibit Flip-Flop Integration With Clock Gating Download Download
65. A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS Download Download
66. A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar
Applications
Download Download
67. Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design Download Download
68. Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders Download Download
69. Design and Low Power Magnitude Comparator Download Download
70. Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays Download Download
71. Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications  Download Download
72. A Memristor Based Binary Multiplier Download Download
73. A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies Download Download
74. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar Download Download
75. Delay Analysis for Current Mode Threshold Logic Gate Designs Download Download
76. A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications Download Download
77. Binary Adder Circuit Design Using Emerging MIGFET Devices Download Download
78. CMCS: Current-Mode Clock Synthesis Download Download
79. A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA Download Download
80. 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression  Download Download

 

 

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Last Updated :-10th Oct 2020

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