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application/pdfIEEEIEEE Transactions on Very Large Scale Integration (VLSI) Systems; ;PP;99;10.1109/TVLSI.2019.2892838Error correction code (ECC)memorymultibit upset (MBU)radiation hardened by designsingle-event upset (SEU)SRAM-based field-programmable gate array (FPGA)triple interlocked latch (TILL).Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGATianwen LiHongjin LiuHaigang Yang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems199PP10.1109/TVLSI.2019.28928388
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