High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

Description

📄 Abstract

This work presents a novel full adder circuit based on a hybrid logic structure utilising a compact 10-transistor XOR–XNOR cell, targeting low power and high-speed operation in digital VLSI design. The design is simulated using the HSPICE simulation tool to validate functional accuracy and extract performance metrics such as power consumption and delay. The key contribution lies in achieving a trade-off between transistor count and performance while maintaining proper logic functionality. This makes the design suitable for low-voltage, high-performance arithmetic operations in portable and embedded systems.

✨ Introduction

The full adder is a fundamental building block in digital arithmetic circuits. With the increasing demand for power-efficient and high-speed VLSI systems, there is a constant need to optimise these building blocks. Conventional designs typically use 28T or 20T transistor structures, which increase area and delay. This project introduces an optimised hybrid full adder design using only 10 transistors for XOR–XNOR logic, simulated and validated through HSPICE. The aim is to achieve minimal power consumption without compromising on speed or logical accuracy, supporting modern CMOS design trends.

🎯 Aim

To design, simulate, and validate a high-performance hybrid full adder using a 10T XOR–XNOR logic cell that reduces power consumption and propagation delay, verified through HSPICE simulation results.

🧪 Methodology

1. Design Schematic: Developed transistor-level XOR and XNOR gates using a total of 10 transistors. Combined them to form a full adder circuit.

2. Tool Used: Synopsys HSPICE for schematic entry, simulation, and output waveform analysis.

3. Simulation Setup: Direct .sp file-based simulation. Stimulus applied internally within the .sp code.

4. Output Parameters Extracted:

   • Average Power Consumption (from .lis file)

   • Propagation Delay (tdelay from waveform markers)

   • Job success status (verified via HSPICE logs)

5. Evaluation: Results compared against conventional full adders for performance metrics.

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Get the complete software-based VLSI project with HSPICE code, simulation setup files, output waveforms, performance analysis (power, delay, leakage), and detailed technical explanation.

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Contact us:

👨🏼‍🏭Vipin Kumar Sharma
Ph.D., M.Tech, B.Tech in ECE
🎓Lecturer 🚀#Researcher #VLSI #Embedded

WhatsApp : https://wa.me/919810326343

👨🏼‍🏭Sneha Sharma
Ph.D., M.Tech, B.Tech in ECE
🎓Lecturer 🚀#Researcher #VLSI #Embedded

WhatsApp : https://wa.me/919911331389

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