List of Projects based on VLSI Design
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A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins
Original price was: ₹21,000.00.₹14,990.00Current price is: ₹14,990.00.This project involves the design and HSPICE-based simulation of a reliable 10T SRAM cell optimised for low standby power and improved static noise margins. It features a decoupled read/write path…
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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
Original price was: ₹20,000.00.₹12,000.00Current price is: ₹12,000.00.This VLSI project demonstrates a high-speed, low-power hybrid logic full adder using a 10-transistor XOR–XNOR cell, implemented and simulated in HSPICE. The transistor-level design achieves significant improvements in delay and…