| S.No. |
List of the Project |
| 1. |
Design of Area-Efficient and Highly Reliable RHBD I0T Memory Cell for Aerospace Applications |
|
| 2. |
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits |
|
| 3. |
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion |
|
| 4. |
A Low-Power High-Speed Comparator for Precise Applications |
|
| 5. |
A High-Performance Gated Voltage Level Translator with Integrated Multiplexer |
|
| 6. |
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop |
|
| 7. |
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis |
|
| 8. |
High Performance Ternary Adder using CNTFET |
|
| 9. |
Probability-Driven Multibit Flip-Flop Integration with Clock Gating |
|
| 10. |
High-performance engineered gate transistor-based compact digital circuits |
|
| 11. |
Design and Low Power Magnitude Comparator |
|
| 12. |
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications |
|
| 13. |
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs |
|
| 14. |
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers |
|
| 15. |
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders |
|
| 16. |
Delay Analysis for Current Mode Threshold Logic Gate Designs |
|
| 17. |
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage |
|
| 18. |
A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell |
|
| 19. |
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation |
|
| 20. |
Design for Testability of Sleep Convention Logic |
|
| 21. |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator |
|
| 22. |
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme |
|
| 23. |
Area-Delay Efficient Binary Adders in QCA |
|
| 24. |
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology |
|
