VLSI Design

M.Tech ECE

VLSI Projects List

2018

Tool- Synopsys HSPICE/ Tanner Tools

S.No. List of the Project

1.
Design of Area-Efficient and Highly Reliable RHBD I0T Memory Cell for Aerospace Applications Download

2.
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits Download

3.
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion Download

4.
A Low-Power High-Speed Comparator for Precise Applications Download

5.
A High-Performance Gated Voltage Level Translator with Integrated Multiplexer Download

6.
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop Download

7.
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis Download

8.
High Performance Ternary Adder using CNTFET Download

9.
Probability-Driven Multibit Flip-Flop Integration with Clock Gating Download

10.
High-performance engineered gate transistor-based compact digital circuits Download

11.
Design and Low Power Magnitude Comparator Download

12.
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications Download

13.
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs Download

14.
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers Download

15.
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders Download

16.
Delay Analysis for Current Mode Threshold Logic Gate Designs Download

17.
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage Download

18.
A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell Download

19.
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation Download

20.
Design for Testability of Sleep Convention Logic Download

21.
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Download

22.
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Download

23.
Area-Delay Efficient Binary Adders in QCA Download

24.
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology Download