VLSI Design

Latest VLSI Design Topics  2019-2020

Tool:-HSPICE

Process: – Implementation, Simulation, Training, Thesis Report, Paper Publication

1. A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

2. A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell

3. CNTFET Modeling and Low Power SRAM Cell Design

4. Design and Stability Analysis of CNTFET based SRAM Cell

5. Design of Low Power Logic Gates by Using 32nm and 16nm FinFET Technology

6. FinFET Based 4-BIT Input XOR XNOR Logic Circuit

7. FinFET Device Circuit Co-Design Issues Impact of Circuit Parameters on Delay

8. Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

9. Full-Swing Local Bit line SRAM Architecture Based on the 22-nm FinFET Technology for Low- Voltage Operation

10. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

11. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

12. Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

13. Performance of FinFET Based Adiabatic Logic Circuits

14. Design and optimization of CNTFET based Domino 1- Bit ALU

15. Multiplier FINFET based ultralow power

16. Design and optimization of FINFET based logic circuit

17. Ground bounce noise reduction in digital circuit

18. Schematic and layout design of low power flip flop

19. Design of ultralow power full adder

20. Current mirror based level system using VLSI Technologies

21. D-flip flop optimization

22. A low power single-phase clock distribution using VLSI technology

23. Design of Digital-Serial FIR Filters: Algorithms, Architecture and a CAD Tool

24. Area–Delay–Power Efficient Carry-Select Adder

25. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

26. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation

27. Schematic and Layout Design of low power flip flop

28. Design of Ultra low power full adder Design of adiabatic 32-bit multiplier using modified Booth Algorithm

29. Low-Power and Area-Efficient Carry Select Adder

30. A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

31. Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates

32. Low-Power Pulse-Triggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme

33. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

34. Simulation of 32nm CMOS Inverter

Last Updated:-08th Nov 2019

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