VLSI Design

Latest VLSI Design Topics 2018-2019

These are the best topics if u r interested in Research

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NEW TOPICS 2018-2019

1. A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
2. A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell
3. CNTFET Modeling and Low Power SRAM Cell Design
4. Design and Stability Analysis of CNTFET based SRAM Cell
5. Design of Low Power Logic Gates by Using 32nm and 16nm FinFET Technology
6. FinFET Based 4-BIT Input XOR XNOR Logic Circuit
7. FinFET Device Circuit Co-Design Issues Impact of Circuit Parameters on Delay
8. Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
9. Full-Swing Local Bit line SRAM Architecture Based on the 22-nm FinFET Technology for Low- Voltage Operation
10. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
11. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
12. Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
13. Performance of FinFET Based Adiabatic Logic Circuits

V-1. Design and optimization of CNTFET based Domino 1- Bit ALU
V-2. Multiplier FINFET based ultralow power (Highly Recommended)
V-3. Design and optimization of FINFET based logic circuit
V-4. Ground bounce noise reduction in digital circuit (Highly Recommended)
V-5. Schematic and layout design of low power flip flop
V-6. Design of ultralow power full adder
V-7. Current mirror based level system using VLSI Technologies
V-8. D-flip flop optimization
V-9. A low power single-phase clock distribution using VLSI technology
V-10. Design of Digital-Serial FIR Filters: Algorithms, Architecture and a CAD Tool
V-11. Area–Delay–Power Efficient Carry-Select Adder
V-12. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
V-13. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation
V-14. Schematic and Layout Design of low power flip flop
V-15. Design of Ultra low power full adder Design of adiabatic 32-bit multiplier using modified Booth Algorithm
V-16. Low-Power and Area-Efficient Carry Select Adder
V-17. A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop
V-18. Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide
Fan-In Gates
V-19. Low-Power Pulse-Triggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme
V-20. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
V-21. Simulation of 32nm CMOS Inverter on HSPICE (Highly Recommended)

Workout: – Implementation, Simulation, Training, Thesis, Paper Publication

V-22. Simulation of 32nm CMOS Inverter on HSPICE (Highly Recommended)